Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate or epitaxial layer, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, a thermal oxidation is performed to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material ("or trench fill"), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP), using the barrier nitride layer as a polish stop. After polishing the nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
When creating the STI structure, it is considered desirable for the uppermost surface of the substrate or epitaxial layer to be flush (i.e., coplanar) with the uppermost surface of the trench fill, in order to maximize the performance of the finished device, and to provide a flat topography for subsequent processing steps, particularly photolithographic processing, thereby enabling the formation of minimal dimension features with accuracy and increased manufacturing throughput. However, planarity is adversely affected by conventional techniques, primarily due to the application of the barrier nitride layer as a polish stop.
FIG. 1 illustrates a conventional STI structure formed by conventional STI methodology and comprising substrate 1, oxide liner 2, and insulating material 3. After the insulating material 3 has been applied and planarized using the barrier nitride layer as a polish stop, the barrier nitride layer and pad oxide layer are stripped off, creating a step having a height S between the main surface 1a of the substrate 1 and the uppermost surface 3a of the insulating material 3. Thus, the use of a conventional barrier nitride layer as a polish stop creates a topographical step, rendering it difficult to photolithographically process subsequent layers of the device, particularly in forming features with fine dimensions, thereby adversely affecting process yield and production cost. This problem becomes more acute as circuit geometry is continuously reduced and the height of the step challenges the depth of focus limitations of conventional photolithographic equipment.
In copending Application Ser. No. 08/992,488 filed Dec. 18, 1997 (Attorney Docket No. 1033-309), a method is disclosed for forming an STI structure by omitting the barrier nitride polish stop layer, avoiding the generation of a topographical step and achieving substantial planarity. The disclosed method simplifies the STI formation process by applying the photoresist mask directly to the pad oxide layer formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. The substrate or epitaxial layer is then etched to form a trench. The mask is subsequently removed, an oxide liner is grown in the trench, and the trench is filled with an insulating material. Finally, the insulating material is planarized, as by CMP, down to the main surface, such that the main surface and the uppermost surface of the insulating material are substantially coplanar.
The methodology disclosed in copending Application Ser. No. 08/992,488 (Attorney Docket No. 1033-309) simplifies STI methodology by omitting, the barrier nitride polish stop layer with a corresponding reduction in manufacturing cost, and avoids generating a topographical step, thereby enhancing photolithographic accuracy, particularly with respect to fine circuit geometry. However, when the insulating material is planarized by CMP down to the main surface, damage to the silicon of the main surface may occur due to over-polishing. Such damage may be physical (scratching) or chemical (contamination of the silicon with other materials). In copending Application Ser. No. 08,992,488 (Attorney Docket No. 1033-309), such substrate damage is repaired by performing additional process steps, such as wet or plasma etching to remove a layer and restore fresh silicon at the main surface, or reoxidation and removal of the resulting oxide layer by wet or plasma etching. A further increase in manufacturing throughput can be achieved if such substrate repair procedures can be omitted without adversely impacting device integrity.
There exists a need for a method of manufacturing a semiconductor device with an STI structure, wherein the uppermost surface of the substrate or epitaxial layer is substantially coplanar with the uppermost surface of the trench, without causing damage to the uppermost surface of the substrate or epitaxial layer requiring additional remedial processing.